The present invention relates to a semiconductor device including a bipolar transistor, in particular, a bipolar transistor with high speed characteristics, and to a method of manufacturing such a semiconductor device.
In order to improve the high speed characteristics of a bipolar transistor, it is necessary to form shallow emitter and base diffusion regions. In view of this, a conventional semiconductor device has an emitter electrode comprising a polysilicon layer and an emitter formed in a semiconductor region using the emitter electrode as a diffusion source. A device formed in this manner has the following structure. An n.sup.+ -type buried region is formed in a p-type silicon substrate, and a vertical npn transistor is fabricated on the buried region. The npn transistor consists of an n.sup.- -type epitaxial layer surrounded by a field oxide layer and formed in the buried region, a p.sup.- -type active base region formed on the epitaxial layer, an external base region and an n.sup.+ -type emitter region formed in the active base region, and an n.sup.+ -type collector contact region formed in the buried region to be isolated from the emitter and base regions by an isolation region. The n.sup.+ -type emitter region is connected to an aluminum electrode through a polysilicon layer. An aluminum base electrode is connected to the external base region and the n.sup.+ -type collector contact region. Electrodes consisting of aluminum layers are connected to the collector contact region.
In the vertical transistor of the semiconductor device described above, arsenic is doped in a polysilicon layer forming an emitter electrode, and a shallow n.sup.+ -type emitter region is formed in the active base region using the polysilicon layer as a diffusion source.
In an I.sup.2 L device, a boron-doped polysilicon layer is used as a diffusion source for forming a collector region for the vertical transistor. The polysilicon layer is also used to connect logic gate elements.
A conventional semiconductor device of the type described above, wherein an impurity-doped polysilicon layer is used as an electrode and an impurity region is formed as a diffusion source in a semiconductor region, has the following problems:
For example, when the impurity concentration of the polysilicon forming the emitter electrode of a vertical transistor exceeds a predetermined value, the impurity diffuses anomalously in the base region and it becomes difficult to form a shallow emitter region. Therefore, the impurity concentration of the emitter electrode must be limited to a predetermined range. However, when the impurity concentration is limited in order to obtain a proper emitter diffusion depth, the sheet resistance of the polysilicon layer can become more than 100 .OMEGA./square and high speed operation characteristics may be impaired.
In the case of an I.sup.2 L device, the impurity concentration cannot be increased beyond a predetermined value for the same reason as described above. The resistance of the polysilicon layer and the wiring resistance are increased, thus interfering with high-speed operation. In addition, since a voltage drop occurs between an output electrode of one logic gate element and an input electrode of another logic gate element, a desired output level cannot be obtained and the inverter operation cannot be performed.